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? semiconductor components industries, llc, 2011 june, 2011 ? rev. 24 1 publication order number: ncv4276/d ncv4276, ncv4276a 400 ma low-drop voltage regulator the ncv4276 is a 400 ma output current integrated low dropout regulator family designed for use in harsh automotive environments. it includes wide operating temperature and input voltage ranges. the device is offered with fixed output voltage options of 1.8 v and 2.5 v with 4% output voltage accuracy while the 3.3 v, 5.0 v, and adjustable voltage versions are available either in 2% or 4% output voltage accuracy. it has a high peak input voltage tolerance and reverse input voltage protection. it also provides overcurrent protection, overtemperature protection and inhibit for control of the state of the output voltage. the ncv4276 family is available in dpak and d 2 pak surface mount packages. the output is stable over a wide output capacitance and esr range. features ? 2.5 v and 1.8 v 4% output voltage ? 3.3 v, 5.0 v, and adjustable voltage version (from 2.5 v to 20 v) 4% or 2% output voltage ? 400 ma output current ? 500 mv (max) dropout voltage (5.0 v output) ? inhibit input ? very low current consumption ? fault protection ? +45 v peak transient voltage ? ? 42 v reverse voltage ? short circuit ? thermal overload ? ncv prefix for automotive and other applications requiring site and control changes ? these are pb ? free devices d 2 pak 5 ? pin ds suffix case 936a 1 5 dpak 5 ? pin dt suffix case 175aa 1 5 see detailed ordering and shipping information in the ordering information section on page 23 of this data sheet. ordering information http://onsemi.com see general marking information in the device marking section on page 22 of this data sheet. device marking information
ncv4276, ncv4276a http://onsemi.com 2 ? + i inh q gnd current limit and saturation sense bandgap reference thermal shutdown figure 1. 4276 block diagram error amplifier nc ? + i inh q gnd current limit and saturation sense bandgap reference thermal shutdown figure 2. 4276 adjustable block diagram error amplifier va
ncv4276, ncv4276a http://onsemi.com 3 pin function description pin no. symbol description 1 i input; battery supply input v oltage. 2 inh inhibit; set low ? to inhibit. 3 gnd ground; pin 3 internally connected to heatsink. 4 nc / va not connected for fixed voltage version / voltage adjust input for adjustable voltage version; use an external voltage divider to set the output voltage 5 q output: bypass with a capacitor to gnd. see figures 3 to 8 and regulator stability considerations section. maximum ratings * rating symbol min max unit input v oltage v i ? 42 45 v input peak t ransient v oltage v i ? 45 v inhibit inh voltage v inh ? 42 45 v voltage adjust input va v va ? 0.3 10 v output v oltage v q ? 1.0 40 v ground current i q ? 100 ma input voltage operating range v i v q + 0.5 v or 4.5 v (note 1) 40 v esd susceptibility (human body model) (machine model) (charged device model) ? ? ? 4.5 250 1.25 ? ? ? kv v kv junction t emperature t j ? 40 150 c storage t emperature t stg ? 50 150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. *during the voltage range which exceeds the maximum tested voltage of i, operation is assured, but not specified. wider limits may appl y. thermal dissipation must be observed closely. lead temperature soldering reflow (note 2) lead temperature soldering reflow (smd styles only), leaded, 60 ? 150 s above 183, 30 s max at peak reflow (smd styles only), lead free, 60 ? 150 s above 217, 40 s max at peak wave solder (through hole styles only), 12 sec max t sld ? ? ? 240 265 310 c thermal characteristics characteristic test conditions (typical v alue) unit dpak 5 ? pin p ackage min pad board (note 3) 1 pad board (note 4) junction ? to ? tab (psi ? jlx, jlx ) 4.2 4.7 c/w junction ? to ? ambient (r ja , ja ) 100.9 46.8 c/w d 2 pak 5 ? pin p ackage 0.4 sq. in. spreader board (note 5) 1.2 sq. in. spreader board (note 6) junction ? to ? tab (psi ? jlx, jlx ) 3.8 4.0 c/w junction ? to ? ambient (r ja , ja ) 74.8 41.6 c/w 1. minimum v i = 4.5 v or (v q + 0.5 v), whichever is higher. 2. per ipc / jedec j ? std ? 020c. 3. 1 oz. copper, 0.26 inch 2 (168 mm 2 ) copper area, 0.062 thick fr4. 4. 1 oz. copper, 1.14 inch 2 (736 mm 2 ) copper area, 0.062 thick fr4. 5. 1 oz. copper, 0.373 inch 2 (241 mm 2 ) copper area, 0.062 thick fr4. 6. 1 oz. copper, 1.222 inch 2 (788 mm 2 ) copper area, 0.062 thick fr4.
ncv4276, ncv4276a http://onsemi.com 4 electrical characteristics (v i = 13.5 v; ? 40 c < t j < 150 c; unless otherwise noted.) characteristic symbol test conditions ncv4276 ncv4276a unit min typ max min typ max output output voltage, 5.0 v v ersion v q 5.0 ma < i q < 400 ma, 6.0 v < v i < 28 v 4.8 5.0 5.2 4.9 5.0 5.1 v output voltage, 5.0 v v ersion v q 5.0 ma < i q < 200 ma, 6.0 v < v i < 40 v 4.8 5.0 5.2 4.9 5.0 5.1 v output voltage, 3.3 v v ersion v q 5.0 ma < i q < 400 ma, 4.5 v < v i < 28 v 3.168 3.3 3.432 3.234 3.3 3.366 v output voltage, 3.3 v v ersion v q 5.0 ma < i q < 200 ma, 4.5 v < v i < 40 v 3.168 3.3 3.432 3.234 3.3 3.366 v output voltage, 2.5 v v ersion v q 5.0 ma < i q < 400 ma, 4.5 v < v i < 28 v 2.4 2.5 2.6 ? ? ? v output voltage, 2.5 v v ersion v q 5.0 ma < i q < 200 ma, 4.5 v < v i < 40 v 2.4 2.5 2.6 ? ? ? v output voltage, 1.8 v v ersion v q 5.0 ma < i q < 400 ma, 4.5 v < v i < 28 v 1.728 1.8 1.872 ? ? ? v output voltage, 1.8 v v ersion v q 5.0 ma < i q < 200 ma, 4.5 v < v i < 40 v 1.728 1.8 1.872 ? ? ? v output voltage, adjustable version av q 5.0 ma < i q < 400 ma v q +1 < v i < 40 v v i > 4.5 v ? 4% ? +4% ? 2% ? +2% v output current limitation i q v q = 90% v qtyp (v qtyp = 2.5 v for adj version) 400 700 1100 400 700 1100 ma quiescent current (sleep mode) i q = i i ? i q i q v inh = 0 v ? ? 10 ? ? 10 a quiescent current, i q = i i ? i q i q i q = 1.0 ma ? 130 220 ? 130 200 a quiescent current, i q = i i ? i q i q i q = 250 ma ? 10 15 ? 10 15 ma quiescent current, i q = i i ? i q i q i q = 400 ma ? 25 35 ? 25 35 ma dropout voltage, 5.0 v version 3.3 v version 2.5 v version 1.8 v version adjustable v ersion v dr i q = 250 ma, v dr = v i ? v q v i = 5.0 v v i = 4.5 v v i = 4.5 v v i = 4.5 v v i > 4.5 v ? ? ? ? ? 250 ? ? ? 250 500 1.332 2.1 2.772 500 ? ? ? ? ? ? ? ? ? 250 ? ? ? ? 500 mv v v v mv dropout voltage (5.0 v v ersion) v dr i q = 250 ma (note 7) ? ? ? ? 250 500 mv load regulation v q,lo i q = 5.0 ma to 400 ma ? 10 35 ? 3.0 20 mv line regulation v q v i = 12 v to 32 v, i q = 5.0 ma ? 2.5 25 ? 4.0 15 mv power supply ripple rejection psrr f r = 100 hz, v r = 0.5 v pp ? 60 ? ? 70 ? db temperature output voltage drift d vq/dt ? ? 0.5 ? ? 0.5 ? mv/k inhibit inhibit voltage, output high v inh v q v qmin ? 2.8 3.5 ? 2.3 2.8 v inhibit voltage, output low (off) v inh v q 0.1 v 0.5 1.7 ? 1.8 2.2 ? v input current i inh v inh = 5.0 v 5.0 10 20 5.0 10 20 a thermal shutdown thermal shutdown t emperature* t sd i q = 5.0 ma 150 ? 210 150 ? 210 c *guaranteed by design, not tested in production. 7. measured when the output voltage v q has dropped 100 mv from the nominal valued obtained at v = 13.5 v.
ncv4276, ncv4276a http://onsemi.com 5 5.5 ? 45 v input c i1 1.0 f c i2 100 nf i i i inh 1 2 5 4 3 gnd c q 22 f i q q nc output figure 3. applications circuit; fixed voltage version ncv4276 r l i inh input c i1 1.0 f c i2 100 nf i i i inh 1 2 5 4 3 gnd c q 22 f i q q va output figure 4. applications circuit; adjustable voltage version ncv4276 ncv4276a r l i inh r 1 r 2 v q = [(r1 + r2) * v ref ] / r2 c b * c b * ? required if usage of low esr output capacitor c q is demand, see regulator stability considerations section
ncv4276, ncv4276a http://onsemi.com 6 typical performance characteristics 0.01 0.1 1 10 100 0 150 250 350 50 100 200 300 400 esr ( ) c q = 22 f for these output v oltages stable region output current (ma) unstable region 6 v 2.5 v 12 v figure 5. output stability with output capacitor esr, 5.0 v, 3.3 v, 2.5 v and 1.8 v regulator 0.01 0.1 1 10 output current (ma) esr ( ) c q = 22 f for all fixed output voltages stable region 0 150 250 350 50 maximum esr for c q = 22 f 100 200 300 400 figure 6. output stability with output capacitor esr, 5.0 v and 3.3 v regulator esr ( ) figure 7. output stability with output capacitor esr, 2.5 v and 1.8 v regulator figure 8. output stability with output capacitor esr, adjustable regulator unstable region 0.01 0.1 1 10 output current (ma) c q = 10 f for 3.3 v and 5 v fixed output v oltages stable region 0 150 250 350 50 maximum esr for c q = 10 f 100 200 300 400 unstable region 0.01 0.1 1 10 output current (ma) esr ( ) stable region 0 150 250 350 50 maximum esr for c q = 10 f 100 200 300 400 unstable region c q = 10 f for 1.8 v and 2.5 v fixed output v oltages minimum esr for c q = 10 f unstable region unstable region c b capacitor not connected
ncv4276, ncv4276a http://onsemi.com 7 typical performance characteristics ? 4276 version 4.8 4.9 5.0 5.1 5.2 ? 40 0 40 80 120 160 v i = 13.5 v r l = 1000 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 ? 40 0 40 80 120 160 v i = 13.5 v r l = 1 k 3.15 3.20 3.25 3.30 3.35 3.40 3.45 ? 40 0 40 120 160 figure 9. output voltage vs. junction temperature, 5.0 v version figure 10. output voltage vs. junction temperature, 1.8 v version figure 11. output voltage vs. junction temperature, 2.5 v version figure 12. output voltage vs. junction temperature, 3.3 v version 0 5 10 15 20 25 30 35 40 45 01020304050 t j = 25 c r l = 20 0 1.0 2.0 3.0 5.0 6.0 7.0 8.0 9.0 10 01020304050 t j = 25 c r l = 20 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 ? 40 0 40 80 120 160 v i = 13.5 v r l = 1 k v i = 13.5 v r l = 1 k 80 4.0 t j , junction temperature ( c) v q , output voltage (v) v i , input voltage (v) i q , current consumption (ma) figure 13. current consumption vs. input voltage, 5.0 v version figure 14. current consumption vs. input voltage, 1.8 v version v i , input voltage (v) i q , current consumption (ma) t j , junction temperature ( c) v q , output voltage (v) t j , junction temperature ( c) v q , output voltage (v) t j , junction temperature ( c) v q , output voltage (v)
ncv4276, ncv4276a http://onsemi.com 8 typical performance characteristics ? 4276 version 0 1.0 5.0 6.0 10 020304050 v i , input voltage (v) i q , current consumption (ma) 0 5.0 10 15 20 25 30 0 10203040 60 v i , input voltage (v) t j = 25 c r l = 20 ? 8 ? 6 ? 4 ? 2 0 2 4 6 ? 50 ? 25 0 25 50 v i , input voltage (v) i i , input current (ma) t j = 25 c r l = 6.8 k figure 15. current consumption vs. input voltage, 2.5 v version figure 16. current consumption vs. input voltage, 3.3 v version figure 17. high voltage behavior 0 100 200 300 400 500 600 700 800 0 1020304050 i q , output current (ma) t j = 25 c v q = 0 v 0 100 200 300 400 500 600 0 50 100 150 200 250 300 350 400 v dr , dropout voltage (mv) i q , output current (ma) t j = 25 c t j = 125 c figure 18. dropout voltage vs. output current, 5.0 v version figure 19. maximum output current vs. input voltage 10 2.0 3.0 4.0 8.0 9.0 7.0 t j = 25 c r l = 20 50 0 10 20 30 40 50 60 0 100 200 300 400 500 600 t j = 25 c v i = 13.5 v figure 20. current consumption vs. output current (high load) i q , current consumption (ma) v i , input voltage (v) i q , output current (ma) i q , current consumption (ma)
ncv4276, ncv4276a http://onsemi.com 9 typical performance characteristics ? 4276 version 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 102030405060 t j = 25 c v i = 13.5 v figure 21. current consumption vs. output current (low load) 0 0.5 1.0 1.5 2.5 3.5 4.0 0 1.0 2.0 3.0 4.0 5.0 6.0 v i , input voltage (v) v q , output voltage (v) t j = 25 c r l = 20 figure 22. output voltage vs. input voltage, 1.8 v version 0 0.5 1.0 2.5 3.5 4.0 5.0 0 1.0 2.0 3.0 4.0 5.0 6.0 v i , input voltage (v) v q , output voltage (v) t j = 25 c r l = 20 figure 23. output voltage vs. input voltage, 2.5 v version 2.0 3.0 1.5 2.0 3.0 4.5 0 1.0 2.0 3.0 4.0 5.0 6.0 0 1.0 2.0 3.0 4.0 5.0 6.0 v i , input voltage (v) v q , output voltage (v) t j = 25 c r l = 20 figure 24. output voltage vs. input voltage, 3.3 v version 0 1 2 3 4 5 6 0246810 v i , input voltage (v) v q , output voltage (v) t j = 25 c r l = 20 figure 25. output voltage vs. input voltage, 5.0 v version ? 10 ? 8.0 ? 6.0 ? 4.0 ? 2.0 0 2.0 4.0 6.0 ? 50 ? 25 0 25 50 v i , input voltage (v) i i , input current (ma) t j = 25 c r l = 6.8 k figure 26. input current vs. input voltage, 5.0 v version i q , output current (ma) i q , current consumption (ma)
ncv4276, ncv4276a http://onsemi.com 10 typical performance characteristics ? 4276 version ? 7.0 ? 6.0 ? 5.0 ? 4.0 ? 3.0 ? 2.0 ? 1.0 1.0 ? 50 ? 25 0 25 50 v i , input voltage (v) i i , input current (ma) t j = 25 c r l = 6.8 k 0 figure 27. input current vs. input voltage , 1.8 v version ? 7.0 ? 6.0 ? 5.0 ? 4.0 ? 3.0 ? 2.0 ? 1.0 1.0 ? 50 ? 25 0 25 50 v i , input voltage (v) i i , input current (ma) t j = 25 c r l = 6.8 k figure 28. input current vs. input voltage, 2.5 v version 0 ? 10 ? 8.0 ? 6.0 ? 4.0 ? 2.0 0 2.0 4.0 6.0 ? 50 ? 25 0 25 50 v i , input voltage (v) i i , input current (ma) t j = 25 c r l = 6.8 k figure 29. input current vs. input voltage, 3.3 v version
ncv4276, ncv4276a http://onsemi.com 11 typical performance characteristics ? 4276a version t j , junction temperature ( c) v i , input voltage (v) 160 120 80 40 0 ? 40 4.8 4.9 5.0 5.1 5.2 10 8.0 6.0 4.0 2.0 0 0 1.0 2.0 3.0 4.0 5.0 6.0 v q , output voltage (v) v i = 13.5 v r l = 1 k v q , output voltage (v) r l = 20 t j = 25 c v i , input voltage (v) 50 40 30 20 10 0 0 10 20 30 40 i q , current consumption (ma) t j = 25 c r l = 20 figure 30. output voltage vs. junction temperature, 5.0 v version t j , junction temperature ( c) v i , input voltage (v) 160 120 80 40 0 ? 40 3.15 3.25 3.30 3.40 3.45 50 40 30 20 10 0 0 1.0 2.0 3.0 4.0 5.0 10 v q , output voltage (v) v i = 13.5 v r l = 1 k i q , current consumption (ma) r l = 20 t j = 25 c v i , input voltage (v) 6.0 4.0 3.0 2.0 1.0 0 0 2.0 3.0 5.0 6.0 v q , output voltage (v) t j = 25 c r l = 20 figure 31. output voltage vs. junction temperature, 3.3 v version figure 32. current consumption vs. input voltage, 5.0 v version figure 33. current consumption vs. input voltage, 3.3 v version 3.35 3.20 4.0 1.0 5.0 6.0 7.0 8.0 9.0 figure 34. low voltage behavior, 3.3 v version figure 35. low voltage behavior, 5.0 v version
ncv4276, ncv4276a http://onsemi.com 12 typical performance characteristics ? 4276a version i q , output current (ma) 400 300 200 100 0 0 100 200 300 400 500 600 v dr , drop voltage (mv) t j = 125 c t j = 25 c v i , input voltage (v) 50 25 0 ? 25 ? 50 ? 10 ? 8.0 ? 6.0 ? 2.0 0 2.0 6.0 i i , input current (ma) r l = 6.8 k t j = 25 c ? 4.0 4.0 v i , input voltage (v) 50 40 30 20 10 0 0 200 400 600 800 i q , output current (ma) t j = 25 c v q = 0 v figure 36. input current vs. input voltage, 5.0 v version i q , output current (ma) 600 500 400 300 200 100 0 0 10 20 30 40 50 60 i q , output current (ma) 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1.2 1.4 1.6 i q , current consumption (ma) v i = 13.5 v t j = 25 c 1.0 i q , current consumption (ma) v i = 13.5 v v i , input voltage (v) 50 25 0 ? 25 ? 50 ? 10 ? 8.0 ? 6.0 ? 2.0 0 2.0 i i , input current (ma) r l = 6.8 k t j = 25 c ? 4.0 figure 37. input current vs. input voltage, 3.3 v version figure 38. dropout voltage vs. output current figure 39. maximum output current vs. input voltage figure 40. current consumption vs. output current (high load) figure 41. current consumption vs. output current (low load)
ncv4276, ncv4276a http://onsemi.com 13 typical performance characteristics ? adjustable version 2.45 2.46 2.47 2.51 2.55 ? 40 0 40 80 120 160 t j , junction temperature ( c) v q , output voltage (v) v i = 13.5 v, r l = 1 k 0 0.5 1 1.5 2 2.5 3 3.5 4 02 46 810 v i , input voltage (v) v q , output voltage (v) t j = 25 c r l = 20 figure 42. output voltage vs. junction temperature, adjustable version 2.48 2.49 2.50 2.52 2.53 2.54 0 0.5 1.0 1.5 2.0 3.0 5.0 0 1020304050 v i , input voltage (v) t j = 25 c r l = 20 figure 43. current consumption vs. input voltage, adjustable version 3.5 4.0 2.5 4.5 ? 18 ? 16 ? 14 ? 8 ? 6 ? 4 2 ? 50 ? 25 0 25 v i , input voltage (v) i i , input current (ma) t j = 25 c r l = 6.8 k 50 ? 12 ? 10 ? 2 0 figure 44. low voltage behavior, adjustable version figure 45. high voltage behavior, adjustable version i q , current consumption (ma)
ncv4276, ncv4276a http://onsemi.com 14 typical performance characteristics ? adjustable version 0 0.2 0.4 1.6 0 10203040 60 i q , output current (ma) t j = 25 c 0 100 200 300 400 500 600 0 50 100 150 350 400 i q , output current (ma) v dr , dropout voltage (mv) t j = 25 c v i = 13.5 v figure 46. dropout voltage vs. output current, regulator set at 5.0 v, adjustable version 0.6 0.8 1.0 1.2 1.4 50 200 250 300 t j = 125 c 0 100 200 300 400 500 800 0 1020304050 v i , input voltage (v) i q , output current (ma) t j = 25 c v q = 0 v figure 47. maximum output current vs. input voltage, adjustable version 600 700 0 10 20 30 40 50 60 0 100 200 300 400 i q , output current (ma) i q , current consumption (ma) t j = 25 c v i = 13.5 v figure 48. current consumption vs. output current (high load), adjustable version 500 600 figure 49. current consumption vs. output current (low load), adjustable version i q , current consumption (ma)
ncv4276, ncv4276a http://onsemi.com 15 circuit description the ncv4276 is an integrated low dropout regulator that provides a regulated voltage at 400 ma to the output. it is enabled with an input to the inhibit pin. the regulator voltage is provided by a pnp pass transistor controlled by an error amplifier with a bandgap reference, which gives it the lowest possible dropout voltage. the output current capability is 400 ma, and the base drive quiescent current is controlled to prevent oversaturation when the input voltage is low or when the output is overloaded. the regulator is protected by both current limit and thermal shutdown. thermal shutdown occurs above 150 c to protect the ic during overloads and extreme ambient temperatures. regulator the error amplifier compares the reference voltage to a sample of the output voltage (v q ) and drives the base of a pnp series pass transistor via a buffer. the reference is a bandgap design to give it a temperature ? stable output. saturation control of the pnp is a function of the load current and input voltage. oversaturation of the output power device is prevented, and quiescent current in the ground pin is minimized. see figure 4, test circuit, for circuit element nomenclature illustration. regulator stability considerations the input capacitors (c i1 and c i2 ) are necessary to stabilize the input impedance to avoid voltage line influences. using a resistor of approximately 1.0 in series with c i2 can stop potential oscillations caused by stray inductance and capacitance. the output capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures ( ? 25 c to ? 40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturer?s data sheet usually provides this information. the value for the output capacitor c q , shown in figure 3, should work for most applications; see also figures 5 to 8 for output stability at various load and output capacitor esr conditions. stable region of esr in figures 5 to 8 shows esr values at which the ldo output voltage does not have any permanent oscillations at any dynamic changes of output load current. marginal esr is the value at which the output voltage waving is fully damped during four periods after the load change and no oscillation is further observable. esr characteristics were measured with ceramic capacitors and additional series resistors to emulate esr. low duty cycle pulse load current technique has been used to maintain junction temperature close to ambient temperature. minimum esr for c q = 22 f is native esr of ceramic capacitor with which the fixed output voltage devices are performing stable. murata ceramic capacitors were used, grm32er71c226ke18 (22 f, 16 v, x7r, 1210), grm31cr71c106kac7 (10 f, 16 v, x7r, 1206). calculating bypass capacitor if usage of low esr ceramic capacitors is demand in case of adjustable regulator, connect the bypass capacitor c b between voltage adjust pin and q pin according to applications circuit at figure 4. parallel combination of bypass capacitor c b with the feedback resistor r 1 contributes in the device transfer function as an additional zero and affects the device loop stability, therefore its value must be optimized. attention to the output capacitor value and its esr must be paid. see also stability in high speed linear ldo regulators application note, and8037/d for more information. optimal value of bypass capacitor is given by following expression c b 1 2 f z r 1 (f) where r 1 = the upper feedback resistor f z = the frequency of the zero added into the device transfer function by r 1 and c b external components. set the r 1 resistor according to output voltage requirement. chose the f z with regard on the output capacitance c q , refer to the table below. c q ( f) 10 22 47 100 f z range (khz) 20 - 50 14 - 35 10 - 20 7 ? 14 ceramic capacitors and its part numbers listed bellow have been used as low esr output capacitors c q from the table above to define the frequency ranges of additional zero required for stability. grm31cr71c106kac7 (10 f, 16 v, x7r, 1206) grm32er71c226ke18 (22 f, 16 v, x7r, 1210) grm32er61c476me15 (47 f, 16 v, x5r, 1210) grm32er60j107me20 (100 f, 6.3 v, x5r, 1210) inhibit input the inhibit pin is used to turn the regulator on or off. by holding the pin down to a voltage less than 0.5 v (or 1.8 v for ncv4276a parts), the output of the regulator will be turned off. during startup transient the regulator is off at input voltage slew rates faster than 30 v/ s. when the voltage on the inhibit pin is greater than 3.5 v (or 2.8 v for ncv4276a parts), the output of the regulator will be enabled to power its output to the regulated output voltage. the inhibit pin may be connected directly to the input pin to give constant enable to the output regulator.
ncv4276, ncv4276a http://onsemi.com 16 setting the output voltage (adjustable version) the output voltage range of the adjustable version can be set between 2.5 v and 20 v. this is accomplished with an external resistor divider feeding back the voltage to the ic back to the error amplifier by the voltage adjust pin va. the internal reference voltage is set to a temperature stable reference of 2.5 v. the output voltage is calculated from the following formula. ignoring the bias current into the va pin: v q [(r1 r2) * v ref ] r2 use r2 < 50 k to avoid significant voltage output errors due to va bias current. connecting va directly to q without r1 and r2 creates an output voltage of 2.5 v. designers should consider the tolerance of r1 and r2 during the design phase. the input voltage range for operation (pin 1) of the adjustable version is between (v q + 0.5 v) and 40 v. internal bias requirements dictate a minimum input voltage of 4.5 v. the dropout voltage for output voltages less than 4.0 v is (4.5 v ? v q ).
ncv4276, ncv4276a http://onsemi.com 17 calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 50) is: p d(max) [v i(max) v q(min) ]i q(max) (1) v i(max) i q where v i(max) is the maximum input voltage, v q(min) is the minimum output voltage, i q(max) is the maximum output current for the application, i q is the quiescent current the regulator consumes at i q(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: r ja 150 o c t a p d (2) the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. smart regulator ? iq control features i q i i figure 50. single output regulator with key performance parameters labeled v i v q } heatsinks a heatsink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (3) where r jc is the junction ? to ? case thermal resistance, r cs is the case ? to ? heatsink thermal resistance, r sa is the heatsink ? to ? ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in data sheets of heatsink manufacturers. thermal, mounting, and heatsinking considerations are discussed in the on semiconductor application note an1040/d.
ncv4276, ncv4276a http://onsemi.com 18 thermal model a discussion of thermal modeling is in the on semi conductor web site: http://www.onsemi.com/pub/collateral/br1487 ? d.pdf. table 1. dpak 5 ? lead thermal rc network models drain copper area (1 oz thick) 168 mm 2 736 mm 2 168 mm 2 736 mm 2 (spice deck format) cauer network foster network 168 mm 2 736 mm 2 units ta u ta u units c_c1 junction gnd 1.00e ? 06 1.00e ? 06 w ? s/c 1.36e ? 08 1.361e ? 08 sec c_c2 node1 gnd 1.00e ? 05 1.00e ? 05 w ? s/c 7.41e ? 07 7.411e ? 07 sec c_c3 node2 gnd 6.00e ? 05 6.00e ? 05 w ? s/c 1.04e ? 05 1.029e ? 05 sec c_c4 node3 gnd 1.00e ? 04 1.00e ? 04 w ? s/c 3.91e ? 05 3.737e ? 05 sec c_c5 node4 gnd 4.36e ? 04 3.64e ? 04 w ? s/c 1.80e ? 03 1.376e ? 03 sec c_c6 node5 gnd 6.77e ? 02 1.92e ? 02 w ? s/c 3.77e ? 01 2.851e ? 02 sec c_c7 node6 gnd 1.51e ? 01 1.27e ? 01 w ? s/c 3.79e+00 9.475e ? 01 sec c_c8 node7 gnd 4.80e ? 01 1.018 w ? s/c 2.65e+01 1.173e+01 sec c_c9 node8 gnd 3.740 2.955 w ? s/c 8.71e+01 8.59e+01 sec c_c10 node9 gnd 10.322 0.438 w ? s/c sec 168 mm 2 736 mm 2 r?s r?s r_r1 junction node1 0.015 0.015 c/w 0.0123 0.0123 c/w r_r2 node1 node2 0.08 0.08 c/w 0.0585 0.0585 c/w r_r3 node2 node3 0.4 0.4 c/w 0.0304 0.0287 c/w r_r4 node3 node4 0.2 0.2 c/w 0.3997 0.3772 c/w r_r5 node4 node5 2.97519 2.6171 c/w 3.115 2.68 c/w r_r6 node5 node6 8.2971 1.6778 c/w 3.571 1.38 c/w r_r7 node6 node7 25.9805 7.4246 c/w 12.851 5.92 c/w r_r8 node7 node8 46.5192 14.9320 c/w 35.471 7.39 c/w r_r9 node8 node9 17.7808 19.2560 c/w 46.741 28.94 c/w r_r10 node9 gnd 0.1 0.1758 c/w c/w note: bold face items represent the package without the external thermal system. junction r 1 c 1 c 2 r 2 c 3 r 3 c n r n time constants are not simple rc products. amplitudes of mathematical solution are not the resistance values. ambient (thermal ground) figure 51. grounded capacitor thermal network (?cauer? ladder) junction r 1 c 1 c 2 r 2 c 3 r 3 c n r n each rung is exactly characterized by its rc ? product time constant; amplitudes are the resistances. ambient (thermal ground) figure 52. non ? grounded capacitor thermal ladder (?foster? ladder)
ncv4276, ncv4276a http://onsemi.com 19 table 2. d 2 pak 5 ? lead thermal rc network models drain copper area (1 oz thick) 241 mm 2 788 mm 2 241 mm 2 788 mm 2 (spice deck format) cauer network foster network 241 mm 2 653 mm 2 units ta u ta u units c_c1 junction gnd 1.00e ? 06 1.00e ? 06 w ? s/c 1.361e ? 08 1.361e ? 08 sec c_c2 node1 gnd 1.00e ? 05 1.00e ? 05 w ? s/c 7.411e ? 07 7.411e ? 07 sec c_c3 node2 gnd 6.00e ? 05 6.00e ? 05 w ? s/c 1.005e ? 05 1.007e ? 05 sec c_c4 node3 gnd 1.00e ? 04 1.00e ? 04 w ? s/c 3.460e ? 05 3.480e ? 05 sec c_c5 node4 gnd 2.82e ? 04 2.87e ? 04 w ? s/c 7.868e ? 04 8.107e ? 04 sec c_c6 node5 gnd 5.58e ? 03 5.95e ? 03 w ? s/c 7.431e ? 03 7.830e ? 03 sec c_c7 node6 gnd 4.25e ? 01 4.61e ? 01 w ? s/c 2.786e+00 2.012e+00 sec c_c8 node7 gnd 9.22e ? 01 2.05 w ? s/c 2.014e+01 2.601e+01 sec c_c9 node8 gnd 1.73 4.88 w ? s/c 1.134e+02 1.218e+02 sec c_c10 node9 gnd 7.12 1.31 w ? s/c sec 241 mm 2 653 mm 2 r?s r?s r_r1 junction node1 0.015 0.0150 c/w 0.0123 0.0123 c/w r_r2 node1 node2 0.08 0.0800 c/w 0.0585 0.0585 c/w r_r3 node2 node3 0.4 0.4000 c/w 0.0257 0.0260 c/w r_r4 node3 node4 0.2 0.2000 c/w 0.3413 0.3438 c/w r_r5 node4 node5 1.85638 1.8839 c/w 1.77 1.81 c/w r_r6 node5 node6 1.23672 1.2272 c/w 1.54 1.52 c/w r_r7 node6 node7 9.81541 5.3383 c/w 4.13 3.46 c/w r_r8 node7 node8 33.1868 18.9591 c/w 6.27 5.03 c/w r_r9 node8 node9 27.0263 13.3369 c/w 60.80 29.30 c/w r_r10 node9 gnd 1.13944 0.1191 c/w c/w note: bold face items represent the package without the external thermal system. the cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. the foster networks, though when sorted by time constant (as above) bear a rough correlation with the cauer networks, are really only convenient mathematical models. cauer networks can be easily implemented using circuit simulating tools, whereas foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: r(t) n i 1 r i
1 ? e ? t tau i
ncv4276, ncv4276a http://onsemi.com 20 110 150 figure 53. ja vs. copper spreader area, dpak 5 ? lead figure 54. ja vs. copper spreader area, d 2 pak 5 ? lead 100 90 80 70 60 50 40 30 200 250 300 350 400 450 500 550 600 650 700 750 copper area (mm 2 ) ja (c /w) 1 oz 2 oz 110 150 100 90 80 70 60 50 40 30 200 250 300 350 400 450 500 550 600 650 700 750 copper area (mm 2 ) ja (c /w) 1 oz 2 oz 100 10 1.0 0.1 0.01 time (sec) r(t) c /w 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 cu area 167 mm 2 cu area 736 mm 2 figure 55. single ? pulse heating curves, dpak 5 ? lead 100 10 1.0 0.1 0.01 time (sec) r(t) c /w 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 cu area 167 mm 2 cu area 736 mm 2 sqrt(t) figure 56. single ? pulse heating curves, d 2 pak 5 ? lead
ncv4276, ncv4276a http://onsemi.com 21 100 10 1.0 0.1 0.01 pulse width (sec) r ja 788 mm 2 c /w 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 non ? normalized response 50% duty cycle 20% 10% 5% 2% 1% 100 10 1.0 0.1 0.01 pulse width (sec) r ja 736 mm 2 c /w 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 non ? normalized response 50% duty cycle figure 57. duty cycle for 1 spreader boards, dpak 5 ? lead 20% 10% 5% 2% 1% figure 58. duty cycle for 1 spreader boards, d 2 pak 5 ? lead
ncv4276, ncv4276a http://onsemi.com 22 76axxg alyww 1 1 nc v4276a ? xx awlywwg ncv4276a ncv4276a d 2 pak 5 ? pin ds suffix case 936a dpak 5 ? pin dt suffix case 175aa marking diagrams 1 1 4276xg alyww nc v4276 ? xx awlywwg ncv4276 ncv4276 d 2 pak 5 ? pin ds suffix case 936a dpak 5 ? pin dt suffix case 175aa a = assembly location wl, l = wafer lot y = year ww = work week g = pb ? free device x, xx = voltage ratings as indicated below *tab is connected to pin 3 on all packages. dpak xx = aj (adj. v oltage) xx = 50 (5.0 v) xx = 33 (3.3 v) d 2 pak xx = aj (adj. v oltage) xx = 50 (5.0 v) a ? version dpak x = v (adj. v oltage) x = 5 (5.0 v) x = 3 (3.3 v) d 2 pak xx = aj (adj. v oltage) xx = 50 (5.0 v) xx = 33 (3.3 v) xx = 25 (2.5 v) xx = 18 (1.8 v) non ? a ? version
ncv4276, ncv4276a http://onsemi.com 23 ordering information device output v oltage accuracy output v oltage package shipping ? ncv4276dt50rkg 4% 5.0 v dpak, 5 ? pin (pb ? free) 2500 / tape & reel ncv4276ds50g d 2 pak, 5 ? pin (pb ? free) 50 units / rail ncv4276ds50r4g d 2 pak, 5 ? pin (pb ? free) 800 / tape & reel ncv4276dt33rkg 3.3 v dpak, 5 ? pin (pb ? free) 2500 / tape & reel ncv4276ds33g d 2 pak, 5 ? pin (pb ? free) 50 units / rail ncv4276ds33r4g d 2 pak, 5 ? pin (pb ? free) 800 / tape & reel ncv4276ds25g 2.5 v d 2 pak, 5 ? pin (pb ? free) 50 units / rail ncv4276ds25r4g d 2 pak, 5 ? pin (pb ? free) 800 / tape & reel ncv4276ds18g 1.8 v d 2 pak, 5 ? pin (pb ? free) 50 units / rail ncv4276ds18r4g d 2 pak, 5 ? pin (pb ? free) 800 / tape & reel ncv4276dtadjrkg adjustable dpak, 5 ? pin (pb ? free) 2500 / tape & reel ncv4276dsadjg d 2 pak, 5 ? pin (pb ? free) 50 units / rail ncv4276dsadjr4g 800 / tape & reel ncv4276adt33rkg 2% 3.3 v dpak, 5 ? pin (pb ? free) 2500 / tape & reel ncv4276adt50rkg 5.0 v dpak, 5 ? pin (pb ? free) 2500 / tape & reel ncv4276ads50g d 2 pak, 5 ? pin (pb ? free) 50 units / rail ncv4276ads50r4g 800 / tape & reel ncv4276adtadjrkg adjustable dpak, 5 ? pin (pb ? free) 2500 / tape & reel ncv4276adsadjg d 2 pak, 5 ? pin (pb ? free) 50 units / rail NCV4276ADSADJR4G 800 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd801 1/d.
ncv4276, ncv4276a http://onsemi.com 24 package dimensions d a k b r v s f l g 5 pl m 0.13 (0.005) t e c u j h ? t ? seating plane z dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.020 0.028 0.51 0.71 e 0.018 0.023 0.46 0.58 f 0.024 0.032 0.61 0.81 g 0.180 bsc 4.56 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.102 0.114 2.60 2.89 l 0.045 bsc 1.14 bsc r 0.170 0.190 4.32 4.83 s 0.025 0.040 0.63 1.01 u 0.020 ??? 0.51 ??? v 0.035 0.050 0.89 1.27 z 0.155 0.170 3.93 4.32 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. r1 0.185 0.210 4.70 5.33 r1 1234 5 dpak 5, center lead crop dt suffix case 175aa ? 01 issue a 6.4 0.252 0.8 0.031 10.6 0.417 5.8 0.228 scale 4:1
mm inches 0.34 0.013 5.36 0.217 2.2 0.086 soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d.
ncv4276, ncv4276a http://onsemi.com 25 package dimensions d 2 pak 5 case 936a ? 02 issue c 5 ref a 123 k b s h d g c e m l p n r v u terminal 6 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. tab contour optional within dimensions a and k. 4. dimensions u and v establish a minimum mounting surface for terminal 6. 5. dimensions a and b do not include mold flash or gate protrusions. mold flash and gate protrusions not to exceed 0.025 (0.635) maximum. dim a min max min max millimeters 0.386 0.403 9.804 10.236 inches b 0.356 0.368 9.042 9.347 c 0.170 0.180 4.318 4.572 d 0.026 0.036 0.660 0.914 e 0.045 0.055 1.143 1.397 g 0.067 bsc 1.702 bsc h 0.539 0.579 13.691 14.707 k 0.050 ref 1.270 ref l 0.000 0.010 0.000 0.254 m 0.088 0.102 2.235 2.591 n 0.018 0.026 0.457 0.660 p 0.058 0.078 1.473 1.981 r 5 ref s 0.116 ref 2.946 ref u 0.200 min 5.080 min v 0.250 min 6.350 min 45 m 0.010 (0.254) t ? t ? optional chamfer 8.38 0.33 1.016 0.04 16.02 0.63 10.66 0.42 3.05 0.12 1.702 0.067 scale 3:1
mm inches soldering footprint on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a s ituation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncv4276/d smart regulator is a registered trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc a sales representative

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